1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a power supply circuit which is arranged on the same chip as a non-threshold logic (NTL) circuit and which supplies power to the NTL circuit such that the NTL gate circuits in the NTL circuit can operate stably.
2. Description of Related Art
A conventional non-threshold logic (NTL) circuit is supplied with a voltage between a power supply line on a high voltage VCC side and a line on a low voltage GND side, as shown in FIG. 1. FIG. 2 illustrates a part of the NTL circuit of FIG. 1 in which two stages of NTL inverter circuits 111 and 112 are connected in series. The operation will be described below. When a voltage V.sub.IN of a high level is inputted to a first stage of NTL inverter circuit 111, an NPN bipolar transistor T101 is turned on, so that a voltage obtained by subtracting base-emitter forward direction bias V.sub.BE from the inputted voltage V.sub.IN is applied to a resistor R102 having the resistance of r.sub.1. Accordingly, the current I flowing through the NPN bipolar transistor T101 is given as follows. EQU I=(V.sub.IN -V.sub.BE)/r.sub.1
Thus, the following voltage drop V is generated at a resistor R101 having the resistance r.sub.2. EQU V=(r.sub.2 /r.sub.1).times.(V.sub.IN -V.sub.BE)
Accordingly, the following voltage of a low level is outputted from an emitter follower circuit 101 of the first stage of NTL inverter circuit. EQU V.sub.OL =V.sub.CC -(r.sub.2 /r.sub.1).times.(V.sub.IN -V.sub.BE)-V.sub.BE
where V.sub.CC is a power supply voltage from an external power source on the higher voltage side. The voltage V.sub.OL is inputted to the second stage 112 of NTL inverter circuit so that an NPN bipolar transistor T103 is turned off. As a result, the second stage of NTL inverter circuit 112 outputs the following output V.sub.OH of a high level through an emitter follower circuit 102. EQU V.sub.OH =V.sub.CC -V.sub.BE
Next, the operation when the voltage V.sub.IN of a low level is inputted to the first stage of NTL inverter circuit 111 will be described below. When the voltage V.sub.IN is inputted, since the transistor T101 is turned off, the first stage of NTL inverter circuit 111 outputs the following voltage V.sub.OH of a high level from the emitter follower circuit 101. EQU V.sub.OH =V.sub.CC -V.sub.BE
The voltage V.sub.OH of the high level is inputted to the second stage of NTL inverter circuit 112 such that the NPN bipolar transistor T103 is turned on. The operation of the second stage of NTL inverter circuit 112 at this time is the same as that when the voltage V.sub.IN of the high level is inputted to the first stage of NTL inverter circuit 111.
The condition that an NTL gate circuit can operate normally will be described, using the second stage of NTL inverter circuit 112 of FIG. 2. When a voltage of a low level is inputted to the transistor T103 of the second stage of NTL inverter circuit 112, the NPN bipolar transistor T103 must be reliably or completely turned off. If the transistor T103 is not completely turned off, the output of the high level is not precisely outputted, so that the logical swing width is made narrower. Therefore, the voltage V.sub.OL needs to satisfy the following equation (1). EQU V.sub.OL =V.sub.CC -(r.sub.2 /r.sub.1).times.(V.sub.OH -V.sub.BE)-V.sub.BE &lt;V1&lt;V.sub.BE ( 1)
Where V1 is the upper limit of the logic low level in the NTL gate circuit. Here, since EQU V.sub.OH =V.sub.CC -V.sub.BE, EQU V.sub.CC -(r.sub.2 /r.sub.1).times.(V.sub.CC -2V.sub.BE)-V.sub.BE .ltoreq.V1&lt;V.sub.BE ( 2)
However, if the input to the second stage of NTL inverter circuit 112 is too low, the timing when the transistor T103 is turned on delays so that the operation speed of the second stage of NTL inverter circuit 112 is decreased. Therefore, the following relation (3) is to be satisfied. EQU 0&lt;V2.ltoreq.V.sub.CC -(r.sub.2 /r.sub.1).times.(V.sub.CC -2V.sub.BE)-V.sub.BE ( 3)
where V2 is the lower limit of the logic low level in the NTL gate circuit. In this manner, it is the condition for normal operation of the NTL gate circuit to satisfy the equations (2) and (3) at a time. EQU 0&lt;V2&lt;V.sub.CC -(r.sub.2 /r.sub.1).times.(V.sub.CC -2V.sub.BE)-V.sub.BE .ltoreq.V1&lt;V.sub.BE ( 4)
Here, V.sub.BE takes an extremely stable value because of the characteristics of bipolar transistor and it is made possible to increase the ratio of r.sub.1 and r.sub.2 with high precision using digital resistors. The digital resistor is obtained by connecting a plurality of basic resistors in series or in parallel such that the total resistance is integral times of the resistance of the basic resistor or 1/(integral times of the resistance of the basic resistor). The ratio of digital resistors is substantially constant regardless of the variation of manufacturing process.
As seen from the equation (4), it is very important to control the voltage V.sub.CC supplied externally in order to satisfy the equation (4). The V.sub.CC is normally about 2 V and the base-emitter forward direction voltage is about 0.8 to 0.9 V. Therefore, tt is desirable that the upper limit V1 and lower limit V2 takes values in a range of about 0.6 V to 0.7 V.
Since the power supply voltage is supplied externally in the convention NTL gate circuit, there is a problem in that the operation condition of the NTL gate circuit is shifted out of the above-mentioned equations (2) and (3). The operation margin of the NTL gate circuit is small and the allowable range in power supply voltage is about .+-.0.2 V or below. For instance, assuming that V.sub.BE =0.9 V, V.sub.CC =2.1 V and r.sub.2 /r.sub.1 =1.5, the following result is obtained from the equation (2). ##EQU1## That is, the equations (1) and (2) are satisfied. However, if the voltage V.sub.CC is reduced to 1.8 V, ##EQU2## That is, the equation (1) is not satisfied. This means that the output of a logic low level in a stage of NTL gate circuit cannot completely turn off the input transistor of the next stage of NTL gate circuit. To further say, this means that the logic high level of the NTL gate circuit is equal to the logic low level thereof so that the NTL gate circuit cannot be normally operated. In this manner, if the power supply voltage V.sub.CC is reduced from 2.1 V by 0.3 V, the NTL gate circuit operates erroneously.
Conventional methods for setting a reference voltage in a logic LSI including a non-threshold logic (NTL) circuit and an emiter coupled logic (ECL) circuit are disclosed in Japanese examined Patent Disclosures (JP-B2-Hei4-39805 and JP-B2-Hei4-39806). Technique for using both the NTL circuit and the ECL circuit is disclosed only and the power supply circuit for the NTL circuit is different from the present invention in the structure.